Synchronous circuits rely on precisely synchronized event timing for error-free execution of complex synchronous functions. Accordingly, a single clock signal is often used as a reference to synchronize related events in a given process. The power required to distribute such a clock signal throughout a given circuit represents a significant percentage of the circuit's power requirement, particularly if the clock signal is of a relatively high frequency.
Some processes do not require a continuous, high-speed clock signal. In such cases, providing a high-speed clock signal regardless of need unnecessarily wastes power. Some circuits address this waste with a clock multiplexer that allows the clock-distribution network to distribute a reduced-speed clock in place of the primary clock when speed performance is not required. Other circuits further reduce power consumption by preventing the routing of the primary clock signal when the high-speed clock is not required. Alfke et al. describe one such clock gating circuit in commonly owned U.S. Pat. No. 6,204,695, which issued Mar. 20, 2001.
Reducing power consumption is just one reason for providing a switched clock. Some circuit may have to operate in response to two or more separate clock signals. For example, integrated circuits that operate in accordance with the proposed PCI-X bus interface standard must be able to operate in response to either a 133 MHz clock signal or a 66 MHz clock signal.
FIG. 1A (prior art) depicts a two-to-one clock selection circuit 100 that provides either of two clock signals CLK1 and CLK2 on a clock-distribution node CLK3, and advantageously switches between those two clock signals without generating a glitch on node CLK3. (As with other designations herein, CLK1, CLK2, and CLK3 each refer both to a signal and its corresponding node; whether a given designation refers to a signal or a node will be clear from the context.)
Clock selection circuit 100 includes NAND gates 101–103, D-type flip-flops 111 and 112, 2-to-1 multiplexers 121 and 122, a configuration memory cell 123, inverters 131–134, and n-channel pass transistors 141 and 142. Inverter 134 and NAND gate 103 are connected to form keeper circuit 150.
Clock signal CLK1 is applied to inverting and non-inverting input terminals of multiplexer 121. Multiplexer 121 is controlled by a configuration value stored in configuration memory cell 123. Thus, if configuration memory cell 123 stores a logic “0” value, then multiplexer 121 routes the inverse of clock signal CLK1 (i.e., CLK1b). Conversely, if configuration memory cell 123 stores a logic “1” value, then multiplexer 121 routes the clock signal CLK1. The output terminal of multiplexer 121 is coupled to the clock input terminal of flip-flop 111. In the described embodiment, flip-flop 111 is a rising edge triggered flip-flop. As described below, multiplexer 121 effectively enables flip-flop 111 to be triggered by either the rising edges or the falling edges of the CLK1 signal.
A second clock signal CLK2 is applied to inverting and non-inverting input terminals of multiplexer 122. Multiplexer 122 is also controlled by a configuration value stored in configuration memory cell 123. Thus, if configuration memory cell 123 stores a logic “0” value, then multiplexer 122 routes the inverse of clock signal CLK2 (i.e., CLK2b). Conversely, if configuration memory cell 123 stores a logic “1” value, then multiplexer 122 routes the clock signal CLK2. The output terminal of multiplexer 122 is coupled to the clock input terminal of flip-flop 112. In the described embodiment, flip-flop 112 is a rising edge triggered flip-flop. As described in more detail below, multiplexer 122 effectively enables flip-flop 112 to be triggered by either the rising edges or the falling edges of the CLK2 signal.
A clock select signal SEL is provided to an input terminal of NAND gate 101. The Q output terminal of flip-flop 112, which carries output signal Q112, is coupled to the other input terminal of NAND gate 101. The clock select signal SEL is also provided to inverter 133. In response, inverter 133 provides the inverse of the clock select signal SEL to an input terminal of NAND gate 102. The Q output terminal of flip-flop 111, which carries output signal Q111, is coupled to the other input terminal of NAND gate 102.
NAND gate 101 provides input signal D111 to the D input terminal of flip-flop 111. NAND gate 102 provides input signal D112 to the D input terminal of flip-flop 112. Flip-flop 111 has a reset input terminal (R) coupled to receive a power-on-reset signal POR. Flip-flop 112 has a set input terminal (S) coupled to receive the power-on-reset signal POR.
The output terminals of flip-flops 111 and 112 are further connected to input terminals of inverters 131 and 132, respectively. The output terminals of inverters 131 and 132 are coupled to gate electrodes of pass transistors 141 and 142, respectively. The CLK1 and CLK2 signals are provided to the drain terminals of pass transistors 141 and 142, respectively. The source terminals of pass transistors 141 and 142 are commonly connected to node N1. The signal on node N1 is provided as the output clock signal CLK3.
Node N1 is further coupled to an input terminal of NAND gate 103. The other input terminal of NAND gate 103 is coupled to receive the inverse of the POR signal (i.e., PORb). The output terminal of NAND gate 103 is connected to the input terminal of inverter 134. The output terminal of inverter 134 is connected to node N1. When the PORb signal has a logic high value, NAND gate 103 is configured as an inverter. Under these conditions, NAND gate 103 and inverter 134 form a keeper circuit that is capable of holding the state of the signal on node N1. Note that inverter 134 and NAND gate 103 are designed to be weak relative to pass transistors 141 and 142. As a result, when clock signals CLK1 and CLK2 are driven onto node N1, these clock signals can easily change the state of node N1. For a more detailed description of clock selection circuit 100, see U.S. Pat. No. 6,429,698 to Steven P. Young, issued Aug. 6, 2002, which is incorporated herein by reference.
Clock selection circuit 100 works well in many applications, but has two potential shortcomings. First, switching between clocks requires each of flip-flops 111 and 112 to change state, which in turn requires each flip-flop 111 and 112 to be clocked by respective clock signals CLK1 and CLK2. Clock selection circuit 100 is therefore incapable of switching between clock sources unless both clock sources are producing edges. If, for example, clock signal CLK1 were to fail, selection circuit 100 would be unable to switch to clock signal CLK2. Second, the switching of the selection circuit to CLK2 from CLK1, after the SEL signal, happens only after the CLK1 edge (and the CLK2 edge), which may be undesirable in some applications.
FIG. 1B (prior art) depicts another two-to-one clock selection circuit 151 that provides either of two clock signals CLK1 and CLK2 on a clock-distribution node CLK3, and advantageously switches between those two clock signals without generating a glitch on node CLK3. FIG. 1B has several similarities to FIG. 1A and where the similarities occur the labels are kept the same. FIG. 1B has, however, master-slave latches, i.e., latches 115 and 116 (master) and latches 113 and 114 (slave), instead of flip-flops 111 and 112. Also, the NAND gates 101 and 102 are now between the master and slave latches. In circuit 151 an edge on the first clock is not needed to switch away from the first clock, because the SEL signal is connected to the slave latches. The first clock need only be at the correct level to open the gate of the latch. However, in order to prevent glitches, there must be proper set-up and hold times between the clock signals and the select signal. Circuit 151 is an improvement over circuit 100 in that circuit 151 prevents switching of clocks, when one clock fails, in fewer cases than circuit 100. Circuit 151 also has the advantage of switching immediately away from the first clock as long as the set-up time is met and this may be desirable for some applications. However, the disadvantage is that one must be in the right state for circuit 151 to allow a switch of clocks to occur, and matching the right state of circuit 151 with a clock failure may be difficult for some applications.
There is therefore a need for an improved glitchless clock selection circuit that is capable of switching away from a failed clock, and for which there is no set-up or hold time requirement for the select signal.